In power electronics very often semiconductor chips with vertical transistors like, for example, IGBT transistors are used or, in general, transistors in which at least one electrical contact pad is arranged on a first main face of the semiconductor chip and at least one other electrical contact pad is arranged on a second main face opposite to the first main face. Several ones of these semiconductor chips can be mounted on ceramic substrates or printed circuit boards and electrically connected to form power modules or power systems. In this way, for example, up to 20 power semiconductor chips can be combined and electrically connected with each other to form an electrical circuit.
One example of such modules are the so-called intelligent power modules (IPMs). Before delivering the semiconductor chip modules or the individual semiconductor chips to a customer it is important to know whether the semiconductor chip modules or the individual semiconductor chips are in good order and whether they fulfill predetermined performance criteria. Therefore, a need exists for a practical and efficient method for testing semiconductor chips and/or semiconductor chip modules, in particular those including semiconductor power transistor chips or semiconductor chips including vertical transistor structures.